Nitride III-V compound semiconductor substrate, its manufacturing method, manufacturing method of a semiconductor light emitting device, and manufacturing method of a semiconductor device

ABSTRACT

When GaN or other nitride III-V compound semiconductor layers are grown on a substrate such as a sapphire substrate, thickness x of the substrate relative to thickness y of the nitride III-V compound semiconductor layers is controlled to satisfy 0&lt;y/x≦0.011 and x≧450 μm. Alternatively, if the maximum dimension of the substrate is D (cm), its warpage H is in the range of 0&lt;H≦70×10 −4  (cm), and Z=y/x, D is controlled to satisfy the relation 0&lt;D&lt;(2/CZ)cos −1 (1-HCZ), where C (cm −1 ) is the proportionality constant when the radius of curvature of the substrate ρ (cm) is expressed as 1/ρ=CZ.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] This invention relates to a nitride III-V compound semiconductor substrate, its manufacturing method, a method of manufacturing a semiconductor light emitting device and a method of manufacturing a semiconductor device, which are especially suitable for use in manufacturing semiconductor lasers and light emitting diodes, or electron transporting devices.

[0003] 2. Description of the Related Art

[0004] In recent years, semiconductor lasers using nitride III-V compound semiconductors such as AlGaInN (hereinbelow called GaN compound semiconductor lasers) have been under active researches and developments as hopeful semiconductor lasers capable of emitting light over the range from the blue region to the ultraviolet region necessary for enhancing the density of optical discs. Lately, efforts are being expended to further improvement of their lifetimes and properties toward their practical use.

[0005] When manufacturing such a GaN compound semiconductor laser, a laser structure is most typically formed by crystal growth of a GaN compound semiconductor layer on a sapphire substrate. For example, using a sapphire substrate sized 50 mm (2 inches) in diameter and 430 μm in thickness, a GaN compound semiconductor layer is grown thereon up to a thickness around 7 μm in total.

[0006] However, if a GaN compound semiconductor having a thickness around 7 μm on a sapphire substrate as mentioned above, the sapphire substrate warps due to a difference in thermal expansion coefficient between the sapphire and the nitride III-V compound semiconductor such as GaN. This warpage measures as large as 80 μm.

[0007] This large warpage of the sapphire substrate adversely works against exposure in a manufacturing process of a GaN compound semiconductor laser and polishing of the bottom surface of the sapphire substrate.

[0008] More specifically, in the exposure process, the sapphire substrate, having GaN compound semiconductor layers grown thereon and a resist coated on its surface, undergoes exposure through a photo mask. If the sapphire substrate largely warps as mentioned above, distance between the photo mask and the resist may become uneven within the area of the substrate, or a dimensional deviation may be produced between the photo mask and the substrate within the area of the substrate. Thus the mask cannot accurately fit the entire surface of the substrate. As a result, especially when a base GaN layer is laterally grown on the sapphire substrate by ELO (epitaxial lateral overgrowth) and GaN compound semiconductor layers forming a laser structure are grown thereon by crystal growth, it is difficult to form a ridge in a less-defective region (wing portion) between a seed crystal and a coalescing portion of the lateral growth, and the ridge often deviates from the wing portion. Therefore, this problem adversely affects the laser properties, and in particular, its lifetime, and also degrades the production yield.

[0009] For making cavity edges, it is the most usual way to cleave a sapphire substrate having GaN compound semiconductor layers grown thereon. For easier cleavage, it is necessary to thin the sapphire substrate by partly removing it from the bottom by polishing. However, if the sapphire substrate largely warps as mentioned above, it often cracks during polishing.

[0010] Furthermore, if the warpage of the sapphire substrate is large during crystal growth of the GaN compound semiconductor layers, because of uneven temperature distribution along the plane, the resulting GaN compound semiconductor layers become uneven in composition and thickness.

[0011] Under the circumstances, there is a demand for a technique capable of sufficiently reducing warpage of substrates, namely, not to exceed 70 μm, to remove the above-mentioned problems caused by warpage of sapphire substrates.

OBJECTS AND SUMMARY OF THE INVENTION

[0012] It is therefore an object of the invention to provide a nitride III-V compound semiconductor substrate and its manufacturing method capable of limiting warpage of substrates not to exceed 70 μm.

[0013] A further object of the invention is to provide a method of manufacturing a semiconductor light emitting device that can be used when manufacturing the semiconductor light emitting device by using a nitride III-V compound semiconductor substrate made by forming a nitride III-V compound semiconductor layer on a substrate of a material different from the nitride III-V compound semiconductor layer, and can limit warpage of the substrate not to exceed 70 μm, thereby to successfully carry out exposure in the lithographic process and polishing of the bottom surface of the substrate.

[0014] A still further object of the invention is to provide a method of manufacturing a semiconductor device that can be used when manufacturing the semiconductor device by using a nitride III-V compound semiconductor substrate made by forming a nitride III-V compound semiconductor layer on a substrate of a material different from the nitride III-V compound semiconductor layer, and can limit warpage of the substrate not to exceed 70 μm, thereby to successfully carry out exposure in the lithographic process and polishing of the bottom surface of the substrate.

[0015] The Inventor made vigorous researches for solving the above-indicated problems. Outline of the researches is shown below.

[0016] GaN layers were grown on sapphire substrates sized 430 μm and 700 μm in thickness, and 50 mm in diameter. FIG. 1 shows measured values of thickness of GaN layers and measured values of warpage (H) of the sapphire substrates. For growth of the GaN layers, metal organic chemical vapor deposition (MOCVD) was used. It is appreciated from FIG. 1 that the warpage of the sapphire substrate increases proportionally to the thickness of the GaN layer.

[0017] In case a laser structure of GaN compound semiconductor layers is formed on the sapphire substrate, for the purpose of forming a less-defective layer by using a lateral growth technique such as ELO or preventing the operation voltage from increasing when both the n-side electrode and the p-side electrode are formed on a common plane, thickness of the n-type GaN layer grown as the base layer of the laser structure on the sapphire substrate is preferably not smaller than 3 to 5 μm. However, if the GaN layer is grown by 5 μm on the sapphire substrate sized 430 μm in thickness and 50 mm in diameter, the warpage exceeds 70 μm as shown in FIG. 1. In contrast, if the GaN layer is grown by 5 μm on the sapphire substrate sized 700 μm in thickness and 50 mm in diameter, the warpage largely decreases to around 30 μm. As such, when GaN compound semiconductor layers forming a laser structure (cladding layer, waveguide layer, active layer, and so on, which are approximately 2 μm thick in total) are formed on a 5 μm thick base GaN layer, the increase of warpage of the substrate is small. That is, warpage largely depends on the thickness of the base GaN layer.

[0018]FIG. 2 shows measured values of warpage of diametrically 50 mm long and x(μm) thick sapphire substrates having y(μm) thick GaN layers thereon, putting Z=y/x on the abscissa and warpage H (μm) on the ordinate. It is appreciated from FIG. 2 that the warpage reaches and surpasses 80 μm under Z in excess of 0.013, and it adversely affects the mask-fitting in the photolithographic process and polishing of the substrate bottom surface. If y/x is adjusted not to exceed 0.011, the warpage can be limited not to exceed 70 μm. To ensure that the warpage does not exceed 40 μm to enhance the production yield, Z must be 0.006 or less.

[0019] Basic data of FIGS. 2 and 3 is collectively shown in FIG. 3.

[0020] Also from the viewpoint of improving evenness of the temperature distribution along the substrate plane during crystal growth, warpage of the substrate must be minimized. Evenness of the temperature distribution is required for ensuring evenness of the Al composition distribution of the cladding layer of the GaN compound semiconductor laser, distribution of the thickness of each layer and distribution of composition of the active layer (corresponding to the distribution of the emission wavelength). Especially, the active layer needs accurate temperature control and temperature distribution control because the emission wavelength changes by approximately 1 nm with change of the growth temperature by 1° C. If warpage occurs in the substrate, the temperature distribution on the substrate surface increases, and the composition distribution of the active layer (distribution of the emission wavelength) also increases. This results in increasing the region where the emission wavelength deviates from the desired wavelength and decreasing the production yield. If Z is decreased to 0.011 or less and the warpage is limited not to exceed 70 μm, then the production yield can be enhanced also from the above-mentioned viewpoint.

[0021] On the other hand, warpage of the substrate depends on the substrate size as well. Even when Z is large, if the substrate is small, warpage can be reduced. Taking it into consideration, relation between Z and the substrate diameter D for limiting the warpage H below a certain value was found as Equation (1) below and as shown in FIG. 4.

0<D<(2/CZ)cos⁻¹(1-HCZ)  (1)

[0022] where Z=y/x and C are constants determined by the thickness of the substrate.

[0023] Equation (1) is obtained as follows. Assume here that a substrate having the diameter D (cm) warps as shown in FIG. 5. If the warpage is H (cm), the radius of curvature of the substrate is ρ (cm⁻¹), and the view angle of the full span of the substrate from the curvature center is θ (rad), then they have the following relations.

ρ·θ=D  (2)

H=ρ(1-cos(θ/2))  (3)

[0024] An experiment made by the Inventor demonstrates that the curvature 1/ρ is proportional to Z=(thickness of nitride III-V compound semiconductor layer)/(thickness of substrate)=y/x, and there is following relation.

1/ρ=CZ  (4)

[0025] where C (cm⁻¹) is a proportionality constant that is definitely determined by a fixed thickness of the substrate of a particular material.

[0026] As an example, in case the substrate is a 430 μm thick sapphire substrate and the overlying nitride III-V compound semiconductor layer is a GaN layer, Z and 1/ρ make the relation shown in FIG. 6. At the time the proportionality constant C is C=0.20567 (cm⁻¹).

[0027] From Equations (2), (3) and (4), relation between D and Z is as follows.

D=(2/CZ)cos⁻¹(1-HCZ)  (5)

[0028] By determining the substrate diameter to be smaller than D obtained by Equation (5) for the warpage H given, the warpage of the substrate can be limited not to exceed H. That is, when this substrate diameter is D and taking D>0 into account, by determining the diameter D of the substrate to satisfy

0<D<(2/CZ)cos⁻¹(1-HCZ)  (6)

[0029] the warpage of the substrate can be limited not to exceed H. The condition for limiting the warpage of the substrate not to exceed 70 μm is 0<H≦70×10⁻⁴ (cm), and the condition for limiting the warpage of the substrate not to exceed 40 μm is 0<H≦40×10⁻⁴ (cm).

[0030] Although the foregoing explanation was directed to circular substrates, but the invention is not limited to circular substrates, but it is applicable to other shapes of substrates within the limit not inviting difficulties from the viewpoint of the process and the like. In this case, the maximum dimension along the substrate plane may be regarded as D.

[0031] Further, the foregoing explanation is also applicable to substrates other than sapphire substrates provided those other substrates have a difference in thermal expansion coefficient from that of the nitride III-V compound semiconductor, which is equivalent to or lower than the difference the sapphire substrates have.

[0032] The invention has been made through further researches based on the above-explained researches by the Inventor.

[0033] According to the first aspect of the invention, there is provided a nitride III-V compound semiconductor substrate in which nitride III-V compound semiconductor layers are formed on a substrate of a material different from those of the nitride III-V compound semiconductor layers, comprising:

[0034] 0<y≦0.011 and x≧450 μm

[0035] being satisfied when thickness of the substrate is x (μm) and thickness of the nitride III-V compound semiconductor layers is y (μm).

[0036] According to the second aspect of the invention, there is provided a method of manufacturing a nitride III-V compound semiconductor substrate in which nitride III-V compound semiconductor layers are formed on a substrate of a material different from those of the nitride III-V compound semiconductor layers, comprising:

[0037] 0<y≦0.011 and x≧450 μm

[0038] being satisfied when thickness of the substrate is x (μm) and thickness of the nitride III-V compound semiconductor layers is y (μm).

[0039] According to the third aspect of the invention, there is provided a method of manufacturing a semiconductor light emitting device using a nitride III-V compound semiconductor substrate in which nitride III-V compound semiconductor layers are formed on a substrate of a material different from those of the nitride III-V compound semiconductor layers, comprising:

[0040] just before the start of at least one process, the nitride III-V compound semiconductor substrate satisfying

[0041] 0<y≦0.011 and x≧450 μm

[0042] when thickness of the substrate is x (μm) and thickness of the nitride III-V compound semiconductor layers is y (μm).

[0043] According to the fourth aspect of the invention, there is provided a method of manufacturing a semiconductor device using a nitride III-V compound semiconductor substrate in which nitride III-V compound semiconductor layers are formed on a substrate of a material different from those of the nitride III-V compound semiconductor layers, comprising:

[0044] just before the start of at least one process, the nitride III-V compound semiconductor substrate satisfying

[0045] 0<y≦0.011 and x≧450 μm

[0046] when thickness of the substrate is x (μm) and thickness of the nitride III-V compound semiconductor layers is y (μm).

[0047] In the first to fourth aspects of the invention, the relation 0<y/x≦0.006 is preferably satisfied to limit the warpage of the substrate not to exceed 40 μm.

[0048] According to the fifth aspect of the invention, there is provided a nitride III-V compound semiconductor substrate in which nitride III-V compound semiconductor layers are formed on a substrate of a material different from those of the nitride III-V compound semiconductor layers, comprising:

[0049] 0<D<(2/CZ)cos⁻¹(1-HCZ)

[0050] being satisfied when the maximum dimension of the substrate is D (cm), warpage of the substrate is in the range of 0<H≦70×10⁻⁴ (cm), Z=(thickness of nitride III-V compound semiconductor layers)/(thickness of the substrate), and C (cm⁻¹) is the proportionality constant when the radius of curvature of the substrate ρ (cm) is expressed as 1/ρ=CZ.

[0051] According to the sixth aspect of the invention, there is provided a method of manufacturing a nitride III-V compound semiconductor substrate in which nitride III-V compound semiconductor layers are formed on a substrate of a material different from those of the nitride III-V compound semiconductor layers, comprising:

[0052] 0<D<(2/CZ)cos⁻¹(1-HCZ)

[0053] being satisfied when the maximum dimension of the substrate is D (cm), warpage of the substrate is in the range of 0<H≦70×10⁻⁴ (cm), Z=(thickness of nitride III-V compound semiconductor layers)/(thickness of the substrate), and C (cm⁻¹) is the proportionality constant when the radius of curvature of the substrate ρ (cm) is expressed as 1/ρ=CZ.

[0054] According to the seventh aspect of the invention, there is provided a method of manufacturing a semiconductor light emitting device using a nitride III-V compound semiconductor substrate in which nitride III-V compound semiconductor layers are formed on a substrate of a material different from those of the nitride III-V compound semiconductor layers, comprising:

[0055] just before the start of at least one process, the relation

[0056] 0<D<(2/CZ)cos⁻¹(1-HCZ)

[0057] being satisfied when the maximum dimension of the substrate is D (cm), warpage of the substrate is in the range of 0<H≦70×10⁻⁴ (cm), Z=(thickness of nitride III-V compound semiconductor layers)/(thickness of the substrate), and C (cm⁻¹) is the proportionality constant when the radius of curvature of the substrate ρ (cm) is expressed as 1/ρ=CZ.

[0058] According to the eighth aspect of the invention, there is provided a method of manufacturing a semiconductor device using a nitride III-V compound semiconductor substrate in which nitride III-V compound semiconductor layers are formed on a substrate of a material different from those of the nitride III-V compound semiconductor layers, comprising:

[0059] just before the start of at least one process, the relation

[0060] 0<D<(2/CZ)cos⁻¹(1-HCZ)

[0061] being satisfied when the maximum dimension of the substrate is D (cm), warpage of the substrate is in the range of 0<H≦70×10⁻⁴ (cm), Z=(thickness of nitride III-V compound semiconductor layers)/(thickness of the substrate), and C (cm⁻¹) is the proportionality constant when the radius of curvature of the substrate ρ (cm) is expressed as 1/ρ=CZ.

[0062] In the fifth to eighth aspects of the invention, the warpage H preferably satisfies 0<H≦40×10⁻⁴ (cm).

[0063] In the third, fourth, seventh and eighth aspects of the invention, the warpage of the substrate is preferably limited not to exceed 70 μm, more preferably no to exceed 40 μm, in a process largely affected by warpage of the substrate, such as a photolithographic process especially during its exposure, or just before starting a bottom polishing process.

[0064] In the present invention, the smaller the warpage of the substrate, the easier the process. However, excessive effort of reducing the warpage will results in excessively increasing the substrate thickness or excessively reducing the substrate diameter, and it degrades the productivity. On the other hand, although there is no essential upper limit of the substrate thickness, if the substrate is excessively thick, it takes much time for polishing of the substrate bottom and dicing, and it results in increasing the cost of the substrate itself. From the practical viewpoint, if the substrate is preferably thinner than 1 mm (1000 μm), it is effective to shorten the time required for polishing of the substrate bottom or dicing and to limit the cost of the substrate itself. In case the nitride III-V compound semiconductor to be formed on the substrate is desired to be thicker, thickness of the substrate must be increased unless the substrate size is reduced. Taking these factors into consideration, thickness of the substrate is preferably determined in the range of 600 μm≦x<1000 μm or more preferably in the range of 700 μm≦x<1000 μm. If the substrate is excessively small, each substrate yields fewer semiconductor light emitting devices or semiconductor devices, and the productivity degrades. Therefore, the substrate is preferably sized at least to have an area equivalent to that of a 1-inch substrate in diameter.

[0065] In the present invention, the nitride III-V compound semiconductor is composed of at least one kind of group III elements selected from the group consisting of Ga, Al, In and B, and one or more group V elements including which include at least N and may further include As and/or P. Examples of the nitride III-V compound semiconductor are GaN, AlGaN, AlN, GaInN, AlGaInN, InN, and the like.

[0066] The substrate for growing the nitride III-V compound semiconductor layer can be chosen from various kinds of substrates. For example, a sapphire substrate, SiC substrate, Si substrate, GaAs substrate, GaP substrate, InP substrate, spinel (MgAl₂O₄) substrate or silicon oxide substrate may be used.

[0067] For growth of the nitride III-V compound semiconductor, any appropriate technique such as metal organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxial growth or halide vapor phase epitaxial growth HVPE), for example, may be used.

[0068] The semiconductor light emitting device can be a semiconductor laser or a light emitting diode, for example. Basically, the semiconductor device may be of any type that use the nitride III-V compound semiconductor. For example, it may be a light emitting device such as semiconductor laser or light emitting diode, or an electron transporting device such as FET or heterojunction bipolar transistor.

BRIEF DESCRIPTION OF THE DRAWINGS

[0069]FIG. 1 a schematic diagram that shows relation between thickness of a GaN layer and warpage of a sapphire substrate;

[0070]FIG. 2 is a schematic diagram that shows relation between Z=(thickness of the GaN layer)/(thickness of the sapphire substrate) and warpage of the sapphire substrate;

[0071]FIG. 3 is a schematic diagram that shows basic data of FIGS. 2 and 3;

[0072]FIG. 4 is a schematic diagram that shows relation between Z=(thickness of the GaN layer)/(thickness of the sapphire substrate) and diameter of the sapphire substrate for various values of warpage;

[0073]FIG. 5 is a schematic diagram for explaining the process of introducing Equation (1);

[0074]FIG. 6 is a schematic diagram that shows relation between Z=(thickness of the GaN layer)/(thickness of the sapphire substrate) and curvature 1/ρ of the sapphire substrate;

[0075]FIG. 7 is a cross-sectional view of a GaN compound semiconductor laser to be manufactured according to the first embodiment of the invention, taken along a plane perpendicular to the cavity lengthwise direction;

[0076]FIG. 8 is a cross-sectional view of the GaN compound semiconductor laser to be manufactured according to the first embodiment of the invention, taken along a plane parallel to the cavity lengthwise direction;

[0077]FIG. 9 is a perspective view for explaining a manufacturing method of the GaN compound semiconductor laser according to the first embodiment of the invention;

[0078]FIG. 10 is a perspective view for explaining a manufacturing method of the GaN compound semiconductor laser according to the first embodiment of the invention; and

[0079]FIG. 11 is a perspective view for explaining a manufacturing method of the GaN compound semiconductor laser according to the first embodiment of the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0080] Some embodiments of the invention will be explained below with reference to the drawings.

[0081] For convenience, the structure of a GaN compound semiconductor laser to be manufactured according to the embodiments shown below will be first explained.

[0082]FIGS. 6 and 7 illustrate this GaN compound semiconductor laser. FIG. 6 is its cross-sectional view taken along the plane perpendicular to the cavity lengthwise direction. FIG. 7 is a cross-sectional view taken along the plane parallel to the cavity lengthwise direction. The GaN compound semiconductor laser has a ridge structure and a SCH structure (separate confinement heterostructure).

[0083] As shown in FIGS. 6 and 7, the GaN compound semiconductor laser, formed on a c-plane sapphire substrate 1 via a GaN buffer layer 2 by low temperature growth, includes an undoped GaN layer 3 grown by a lateral growth technique such as ELO, n-type GaN contact layer 4, n-type AlGaN cladding layer 5, n-type GaN waveguide layer 6, active layer 7 having, for example, an undoped In_(x)Ga_(1-x)N/In_(y)Ga_(1-y)N multiquantum well structure, n-type undoped InGaN deterioration preventing layer 8, p-type AlGaN cap layer 9, p-type GaN waveguide layer 10, p-type AlGaN cladding layer 11 and p-type GaN contact layer 12 that are deposited sequentially.

[0084] The undoped GaN buffer layer 2 is 30 nm thick, for example. The undoped GaN layer 3 is 0.5 μm thick, for example. The n-type GaN contact layer 4 is 4 μm thick, for example, and doped with silicon (Si), for example, as the n-type impurity. The n-type AlGaN cladding layer 5 is 1.0 μm thick, for example, and doped with Si, for example, as the n-type impurity. Its Al composition is 0.07, for example. The n-type GaN waveguide layer 6 is 0.1 μm thick, for example, and doped with Si, for example, as the n-type impurity. In the active layer 7 having the undoped In_(x)Ga_(1-x)N/In_(y)Ga_(1-y)N multiquantum well structure, the In_(x)Ga_(1-x)N layer as its well layer is 3.5 nm thick, for example, and x=0.08. The In_(y)Ga_(1-y)N layer as the barrier layer is 7 nm thick, for example, and y=0.02. The active layer 7 includes three well layers.

[0085] The undoped InGaN deterioration preventing layer 8 has a graded structure that monotonously deceases in indium (In) composition gradually from the surface adjacent to the active layer 7 toward the surface adjacent to the p-type AlGaN cap layer 9. Indium (In) composition of the layer 8 at the surface adjacent to the active layer 7 is equal to the indium (In) composition y of the In_(y)Ga_(1-y)N layer as the barrier layer of the active layer 7, and indium (In) composition of the layer 8 at the surface adjacent to the p-type AlGaN cap layer 9 is zero. The undoped InGaN deterioration preventing layer 8 may be, for example, 20 nm thick.

[0086] The p-type AlGaN cap layer 9 is 10 nm thick, for example, and doped with magnesium (Mg), for example, as the p-type impurity. Al composition of the p-type AlGaN cap layer 9 is 0.2, for example. The p-type AlGaN cap layer 9 is used for the purpose of preventing deterioration of the active layer 7 caused by decomposition of In therefrom during growth of the p-type GaN waveguide layer 10, p-type AlGaN cladding layer 11 and p-type GaN contact layer, and for the purpose of preventing overflow of carriers (electrons) from the active layer 7. The p-type GaN waveguide layer 10 is 0.1 μm thick, for example, and doped with Mg, for example as the p-type impurity. The p-type AlGaN cladding layer 11 is 0.5 μm thick, for example, and doped with Mg, for example, as its p-type impurity. Al composition of this layer 11 is 0.07, for example. The p-type GaN contact layer 12 is 0.1 μm thick, for example, and doped with Mg, for example, as the p-type impurity.

[0087] Upper part of the n-type GaN contact layer 4, n-type AlGaN cladding layer 5, n-type GaN waveguide layer 6, active layer 7, undoped InGaN deterioration preventing layer 8, p-type AlGaN cap layer 9, p-type GaN waveguide layer 10 and p-type AlGaN cladding layer 11 are shaped into a mesa configuration of a predetermined width. In this mesa portion, a ridge 13 is made up of upper part of the p-type AlGaN cladding layer 11 and the p-type GaN contact layer 12 to extend in the <1-100>direction, for example. Width of the ridge 13 may 1.6 μm, for example.

[0088] An insulating film 14 such as a SiO₂ film having the thickness of 0.3 μm, for example, is formed to cover the entirety of the mesa portion. The insulating film 14 is used for the purpose of electric insulation and surface protection. The insulating film 14 has formed an opening 14 a in the region above the ridge 13, and a p-side electrode 15 is in contact with the p-type GaN contact layer 12 through the opening 14 a. The p-side electrode 15 has a structure made by sequentially depositing a Pd film, Pt film and Au film that are 10 nm thick, 100 nm thick and 300 nm thick, respectively. On the other hand, the insulating film 14 also has formed an opening 14 b in a predetermined region adjacent to the mesa portion, and an n-side electrode 16 is in contact with the n-type GaN contact layer 4 through the opening 14 b. The n-side electrode 16 has a structure made by sequentially depositing a Ti film, Pt film and Au film that are 10 nm thick, 50 nm thick and 100 nm thick, respectively.

[0089] As shown in FIG. 8, edge coat films 19, 20 are formed on a front-side cavity edge surface 17 and a rear-side cavity edge surface 18, respectively. The front-side edge coat film 19 may be a single-layered Al₂O₃ film adjusted in thickness around 3λ/4n (where λ is the laser oscillation wavelength and n is the refractive index) such that the refractive index of the front-side edge surface becomes 10%, for example. The read-side edge coat film 20 may be an Al₂O₃/TiO₂ multi-layered film adjusted in thickness to a value corresponding to four periods of λ/4n, for example, such that the refractive index of the rear-side edge surface becomes 95%, for example.

[0090] Next explained is a manufacturing method of the GaN compound semiconductor laser according to the first embodiment of the invention.

[0091] This embodiment uses a c-plane sapphire substrate 1 having a thickness x in the range from 600 to 1000 μm, e.g. 640 μm, and the diameter of 50 mm, and satisfies 0<y/x≦0.011 with respect to the thickness y of the GaN compound semiconductor layers grown thereon.

[0092] More specifically, preparing the c-plane sapphire substrate 1 whose surface is cleaned by thermal cleaning beforehand, the undoped GaN buffer layer 2 is grown on the c-plane sapphire substrate 1 by MOCVD under a temperature around 500° C., for example. After that, the undoped GaN layer 3 is grown under the growth temperature 1000° C., for example, by a lateral growth technique such as ELO.

[0093] Subsequently, using MOCVD, the n-type GaN contact layer 4, n-type AlGaN cladding layer 5, n-type GaN waveguide layer 6, active layer 7 having the undoped Ga_(1-x)In_(x)N/Ga_(1-y)In_(y)N multiquantum well structure, undoped InGaN deterioration preventing layer 8, p-type AlGaN cap layer 9, p-type GaN waveguide layer 10, p-type AlGaN cladding layer 11 and p-type GaN contact layer 12 are sequentially grown on the undoped GaN layer 3. For growth of the layers not containing indium (In), namely, the n-type GaN contact layer 4, n-type AlGaN cladding layer 5, n-type GaN waveguide layer 6, p-type AlGaN cap layer 9, p-type GaN waveguide layer 10, p-type AlGaN cladding layer 11 and p-type GaN contact layer 12, the growth temperature adjusted to 1000° C., for example. For growth of the active layer 7 having the Ga_(1-x)In_(x)N/Ga_(1-y)In_(y)N multiquantum well structure, which does not contain indium (In), the growth temperature is adjusted in the range from 700 to 800° C. for example, e.g. at 730° C. for example. For growth of the undoped InGaN deterioration-preventing layer 8, its growth temperature is adjusted at the same value as the growth temperature of the active layer 7, namely, 730° C., for example, at the start of the growth, and thereafter, it is gradually raised linearly, for example, such that it rises up to the same growth temperature as that of the p-type AlGaN cap layer 9, namely 835° C. for example, at the end of the growth.

[0094] As to source materials of these GaN compound semiconductor layers, trimethyl gallium ((CH₃)₃Ga, TMG) is used as the source material of Ga, trimethyl aluminum ((CH₃)₃Al, TMA) is used as the source material of Al, trimethyl indium ((CH₃)₃In, TMI) is used as the source material of In, and NH₃ is used as the source material of N, for example. Carrier gas may be H₂, for example. As to dopants, silane (SiH₄) is used as the n-type dopant, and bis-methylcyclopentadienile magnesium ((CH₃C₅H₄)₂Mg) or bis-cyclopentadienile magnesium ((C₅H₅)₂Mg) is used as the p-type dopant.

[0095] Total thickness of the GaN compound semiconductor layers grown on the c-plane sapphire substrate 1 under the conditions mentioned above amounts 6.4 μm approximately. In this case, y/x becomes y/x=6.4 μm/640 μm=0.01, and the warpage of the c-plane sapphire substrate 1 can be limited not to exceed 70 y/x.

[0096] In the next process, the c-plane sapphire substrate 1 having the GaN compound semiconductor layers grown thereon is taken out of the MOCVD apparatus. Then a SiO₂ film (not shown), 0.1 μm thick, for example is formed on the entire surface of the p-type GaN contact layer 12 by CVD, vacuum evaporation, sputtering, or the like, for example. After that, on this SiO₂ film, a resist pattern (not shown) corresponding to the shape of the mesa portion is formed by photolithography. In this photolithographic process, after a photo resist is coated on the entire substrate surface, it is exposed to light by using a predetermined photo mask in an exposure apparatus. Upon this exposure, since the warpage of the c-plane sapphire substrate 1 is limited not to exceed 70 μm, the mask can fit well over the entire surface of the substrate. After that, using this resist pattern as a mask, the SiO₂ film is etched and patterned by wet etching using an etching liquid of the fluoric acid series, or by RIE using an etching gas containing fluorine, such as CF₄ or CHF₃. Subsequently, using the patterned SiO₂ film as a mask, the structure is etched by RIE, for example, down to the n-type GaN contact layer 4. In this RIE process, a chlorine-series gas may be used as the etching gas, for example. As a result of this etching, upper part of the -type GaN contact layer 4, the n-type AlGaN cladding layer 5, n-type GaN waveguide layer 6, active layer 7, undoped InGaN deterioration-preventing layer 8, p-type AlGaN cap layer 9, p-type GaN waveguide layer 10, p-type AlGaN cladding layer 11 and p-type GaN contact layer 12 are patterned into a mesa configuration.

[0097] After that, the SiO₂ film used as the etching mask is removed, and another SiO₂ film (not shown), 0.2 μm thick for example, is again formed on the entire substrate surface by CVD, vacuum evaporation or sputtering, for example. Thereafter, a resist pattern (not shown) corresponding to the shape of the ridge portion is formed on the SiO₂ film by photolithography. Also in this photolithographic process, since the warpage of the c-plane sapphire substrate is limited not to exceed 70 μm during exposure of the photo resist, the mask can fit well over the entire substrate surface. After that, using this resist pattern as a mask, the SiO₂ film is selectively etched into a pattern corresponding to the ridge portion by wet etching using an etching liquid of the fluoric acid series, or by RIE using an etching gas containing fluorine, such as CF₄ or CHF₃.

[0098] In the next process, using the SiO₂ film as a mask, the p-type AlGaN cladding layer 11 is selectively removed by etching to a predetermined depth to make out the ridge 13. In this RIE process, a chlorine-series gas may be used as the etching gas, for example.

[0099] After that, the SiO₂ film used as the etching mask is removed, and the insulating layer 14 such as a SiO₂ film, 0.3 μm thick for example, is formed on the entire substrate surface by CVD, vacuum evaporation or sputtering, for example.

[0100] Subsequently, a resist pattern (not shown) is formed to cover a region of the insulating film 14 excluding the region for the n-side electrode by photolithography. Also in this photolithographic process, since the warpage of the c-plane sapphire substrate is limited not exceed 70 μm during exposure of the photo resist, the mask can fit well over the entire substrate surface.

[0101] Next using this resist pattern as a mask, the insulating film 14 is selectively etched to form the opening 14 b.

[0102] In the next process, maintaining the resist pattern there, a Ti film, Pt film and Au film are sequentially deposited on the entire substrate surface by vacuum evaporation, for example. Thereafter, the resist pattern is removed together with the overlying part of the Ti film, Pt film and Au film (lift-off). As a result, the n-side electrode 16 is formed in contact with the n-type GaN contact layer 4 through the opening in the insulating film 14. The Ti film, Pt film and Au film forming the n-side electrode 16 are, respectively, 10 nm thick, 50 nm thick and 100 nm thick. An alloying process is next carried out for making ohmic contact of the n-side electrode 16.

[0103] Subsequently, after the opening 14 a is formed by selectively removing the insulating film 14 by etching from above the ridge 13 in a similar process, and p-side electrode 15 having the Pd/Pt/Au structure in contact with the p-type GaN contact layer 12 through the opening 14 a is formed in the same manner as the n-side electrode 16. Thereafter, an alloying process is carried out for making ohmic contact of the p-side electrode 15.

[0104] Subsequently, the c-plane sapphire substrate 1 is polished from its bottom surface to thin it to 100 through 200 μm, for example. Just before this polishing process, the warpage of the c-plane sapphire substrate 1 is limited not to exceed 70 μm. Therefore, the polishing is performed without inviting problems such as cracking of the c-plane sapphire substrate.

[0105] After that, the substrate having the laser structure and the electrode formed thereon is cleaved into bars as shown in FIG. 9, thereby to make out cavity edges 17, 18 as shown in FIGS. 10 and 11. Thereafter, edge coat materials are coated on the cavity edges 17, 18 to protect them. More specifically, as shown in FIG. 18, the edge coat film 19 of the above-mentioned material and thickness is formed on the front-side cavity edge 17, and the edge coat film 20 of the above-mentioned material and thickness is formed on the read-side cavity edge 18. For forming these edge coat films 19, 20, sputtering may be used for example.

[0106] Bars having formed the edge coat films 10, 20 are taken out of the apparatus, and each bar is pelletized to form laser chips as shown in FIGS. 7 and 8.

[0107] Thereafter, each laser chip is packaged to obtain the intended GaN compound semiconductor laser having the ridge structure and SCH structure.

[0108] As explained above, the first embodiment manufacture the GaN compound semiconductor laser by using the c-plane sapphire substrate 1 sized 50 mm in diameter and 640 μm in thickness x, which is thicker than conventional ones, and by growing GaN compound semiconductor layers on the c-plane sapphire substrate 1 such that their total thickness y amounts 6.4 μm, and therefore, it can adjust the ratio y/x to be y/x=6.4/640=0.01 and can limit the warpage of the c-plane sapphire substrate 1 not to exceed 70 μm not only during growth of the GaN compound semiconductor layers but also at the completion of the growth. Thus the embodiment can maintain the warpage of the c-plane sapphire substrate 1 not to exceed 70 μm in the photolithographic process, especially upon exposure, and just before polishing the bottom of the c-plane sapphire substrate 1. As a result, the embodiment can keep the distance between the photo mask and the resist uniform over the substrate area and can prevent dimensional deviation between the photo mask and the substrate over the substrate area such that the mask accurately fits over the entire substrate area. It is therefore possible to make the ridge in the less-defective region between the seed crystal and the meeint portion of the lateral growth, i.e. in the wing portion. Without deviation of the ridge from the wing portion, the embodiment can improve the laser properties, e.g. the lifetime, inter alia, and can improve the production yield. Additionally, the embodiment can prevent the c-plane sapphire substrate 1 from cracking when it is polished from the bottom.

[0109] Moreover, since the embodiment can limit the warpage of the c-plane sapphire substrate 1 as small as 70 μm or less during growth of the GaN compound semiconductor layers as explained above, it ensures uniform temperature distribution a long the plane upon crystal growth of the GaN compound semiconductor layers, thereby ensures the GaN compound semiconductor layers to be uniform in composition and thickness and particularly the active layer to be uniform in composition so as to improve evenness of the emission wavelength.

[0110] With these advantages, the embodiment can manufacture a long-lived, high-performance GaN compound semiconductor laser by high productivity and production yield.

[0111] Next explained is a manufacturing method of a GaN compound semiconductor laser according to the second embodiment of the invention.

[0112] The second embodiment uses a c-plane sapphire substrate 1 having the thickness of 430 μm and having a diameter D satisfying the equation

[0113] 0<D<(2/CZ)cos⁻¹(1-HCZ)

[0114] and grows GaN compound semiconductor layers, 6.4 μm thick in total, on the c-plane sapphire substrate 1 similarly to the first embodiment. If that equation is substituted by C=0.20567 cm^(−1,) H=70 μm=70×10⁻⁴ cm, Z=6.4/430=0.0149, it results in

[0115] 0<D<4.27 cm

[0116] Assume here that D satisfying the inequality is 4 cm. That is, in the second embodiment, a c-plane sapphire substrate 1 having the diameter of 4 cm and the thickness of 430 μm is used to manufacture the GaN compound semiconductor laser.

[0117] The other features of the second embodiment are common to those of the first embodiment, and omitted from explanation.

[0118] The second embodiment also ensures the same advantages as those of the first embodiment.

[0119] Heretofore, embodiments of the invention have been explained specifically. However, the invention is not limited to those embodiments but contemplates various changes and modifications based on the technical concept of the invention.

[0120] For example, numerical values, structures, substrates, source materials, processes, and the like, specifically indicated in conjunction with the first and second embodiments are not but examples, and any appropriate numerical values, structures, substrates, source materials, processes, etc. may be used.

[0121] For example, the first and second embodiments have been explained as first depositing n-type layers of the laser structure on the substrate and thereafter depositing p-type layers. However, the order of deposition may be opposite to first deposit p-type layers on the substrate and thereafter deposit n-type layers.

[0122] Further, the first and second embodiments use the c-plane sapphire substrate, but a SiC substrate, Si substrate or spinel substrate, for example, may be used instead, where appropriate. Furthermore, an AlN buffer layer or AlGaN buffer layer may be used instead of the GaN buffer layer.

[0123] The first and second embodiments have been explained as applying the invention to the manufacture of a GaN compound semiconductor laser of a SCH structure. Instead, the invention is applicable to the manufacture of a GaN compound semiconductor laser of a DH structure (double heterostructure), for example, or to the manufacture of a GaN compound light emitting diode, or further to an electron transporting device using nitride III-V compound semiconductors, such as GaN compound FET, GaN compound heterojunction bipolar transistor (HBT), for example.

[0124] The first and second embodiments have been explained as using H₂ gas as the carrier gas for growth by MOCVD. However, any other appropriate gas such as H₂ with N₂, or mixture with He or Ar gas.

[0125] As described above, according to the invention, when the thickness of the substrate is x (μm), and the thickness of the nitride III-V compound semiconductor layers is y (μm), by adjusting them to satisfy 0<y≦0.011 and x≧450 μm, warpage of the substrate can be limited not to exceed 70 μm. Therefore, the invention can remove various problems caused by warpage of the substrate, such as adverse influences to exposure in the photolithographic process or problems in the bottom polishing process, and thereby ensure high productivity and good yield of long-lived, high-performance semiconductor light emitting devices or semiconductor devices.

[0126] Further, when the maximum dimension of the substrate is D (cm), warpage of the substrate is in the range of 0<H≦70×10⁻⁴ (cm), and Z=(thickness of nitride III-V compound semiconductor layers)/(thickness of the substrate), by adjusting them to satisfy

[0127] 0<D<(2/CZ)cos⁻¹(1-HCZ)

[0128] where C (cm⁻¹) is the proportionality constant when the radius of curvature of the substrate ρ (cm) is expressed as 1/ρ=CZ, the invention can limit the warpage of the substrate not to exceed 70 μm. Therefore, the invention can remove various problems caused by warpage of the substrate, such as adverse influences to exposure in the photolithographic process or problems in the bottom polishing process, and thereby ensure high productivity and good yield of long-lived, high-performance semiconductor light emitting devices or semiconductor devices. 

What is claimed is:
 1. A nitride III-V compound semiconductor substrate in which nitride III-V compound semiconductor layers are formed on a substrate of a material different from those of said nitride III-V compound semiconductor layers, comprising: 0<y≦0.011 and x≧450 μm being satisfied when thickness of said substrate is x (μm) and thickness of said nitride III-V compound semiconductor layers is y (μm).
 2. The nitride III-V compound semiconductor substrate according to claim 1 wherein said x is in the range of 450 μm≦x<1000 μm.
 3. The nitride III-V compound semiconductor substrate according to claim 1 wherein said x/y is in the range of 0<y/x≦0.0066.
 4. The nitride III-V compound semiconductor substrate according to claim 3 wherein said x is in the range of 450 μm≦x<1000 μm.
 5. The nitride III-V compound semiconductor substrate according to claim 1 wherein said substrate is a sapphire substrate.
 6. A nitride III-V compound semiconductor substrate in which nitride III-V compound semiconductor layers are formed on a substrate of a material different from those of said nitride III-V compound semiconductor layers, comprising: 0<D<(2/CZ)cos⁻¹(1-HCZ) being satisfied when the maximum dimension of said substrate is D (cm), warpage of said substrate is in the range of 0<H≦70×10⁻⁴ (cm), Z=(thickness of nitride III-V compound semiconductor layers)/(thickness of the substrate), and C (cm⁻¹) is the proportionality constant when the radius of curvature of said substrate ρ (cm) is expressed as 1/ρ=CZ.
 7. The nitride III-V compound semiconductor substrate according to claim 6 wherein said warpage of said substrate is in the range of 0<H≦40×10⁻⁴ (cm).
 8. The nitride III-V compound semiconductor substrate according to claim 6 wherein said substrate is a sapphire substrate.
 9. The nitride III-V compound semiconductor substrate according to claim 6 wherein C=0.20567.
 10. A method of manufacturing a nitride III-V compound semiconductor substrate in which nitride III-V compound semiconductor layers are formed on a substrate of a material different from those of said nitride III-V compound semiconductor layers, comprising: 0<y≦0.011 and x≧450 μm being satisfied when thickness of said substrate is x (μm) and thickness of said nitride III-V compound semiconductor layers is y (μm).
 11. The method of manufacturing a nitride III-V compound semiconductor substrate according to claim 10 wherein said x is in the range of 450 μm≦x<1000 μm.
 12. The method of manufacturing a nitride III-V compound semiconductor substrate according to claim 10 wherein said x/y is in the range of 0<y/x≦0.0066.
 13. The method of manufacturing a nitride III-V compound semiconductor substrate according to claim 12 wherein said x is in the range of 450 μm≦x<1000 μm.
 14. The method of manufacturing a nitride III-V compound semiconductor substrate according to claim 10 wherein said substrate is a sapphire substrate.
 15. A method of manufacturing a nitride III-V compound semiconductor substrate in which nitride III-V compound semiconductor layers are formed on a substrate of a material different from those of said nitride III-V compound semiconductor layers, comprising: 0<D<(2/CZ)cos⁻¹(1-HCZ) being satisfied when the maximum dimension of said substrate is D (cm), warpage of said substrate is in the range of 0<H≦70×10⁻⁴ (cm), Z=(thickness of nitride III-V compound semiconductor layers)/(thickness of the substrate), and C (cm⁻¹) is the proportionality constant when the radius of curvature of said substrate ρ (cm) is expressed as 1/ρ=CZ.
 16. The method of manufacturing a nitride III-V compound semiconductor substrate according to claim 15 wherein said warpage of said substrate is in the range of 0<H≦40×10⁻⁴ (cm).
 17. The method of manufacturing a nitride III-V compound semiconductor substrate according to claim 15 wherein said substrate is a sapphire substrate.
 18. The method of manufacturing a nitride III-V compound semiconductor substrate according to claim 6 wherein C=0.20567.
 19. A method of manufacturing a semiconductor light emitting device using a nitride III-V compound semiconductor substrate in which nitride III-V compound semiconductor layers are formed on a substrate of a material different from those of said nitride III-V compound semiconductor layers, comprising: just before the start of at least one process, said nitride III-V compound semiconductor substrate satisfying 0<y≦0.011 and x≧450 μm when thickness of said substrate is x (μm) and thickness of said nitride III-V compound semiconductor layers is y (μm).
 20. The method of manufacturing a semiconductor light emitting device according to claim 19 wherein said x is in the range of 450 μm≦x<1000 μm.
 21. The method of manufacturing a semiconductor light emitting device according to claim 19 wherein said x/y is in the range of 0<y/x≦0.0066.
 22. The method of manufacturing a semiconductor light emitting device according to claim 21 wherein said x is in the range of 450 μm≦x<1000 μm.
 23. The method of manufacturing a semiconductor light emitting device according to claim 21 wherein said substrate is a sapphire substrate.
 24. The method of manufacturing a semiconductor light emitting device according to claim 19 wherein said process is a photolithographic process.
 25. The method of manufacturing a semiconductor light emitting device according to claim 19 wherein said process is a polishing process of the bottom surface of said substrate.
 26. A method of manufacturing a semiconductor light emitting device using a nitride III-V compound semiconductor substrate in which nitride III-V compound semiconductor layers are formed on a substrate of a material different from those of said nitride III-V compound semiconductor layers, comprising: just before the start of at least one process, the relation 0<D<(2/CZ)cos⁻¹(1-HCZ) being satisfied when the maximum dimension of said substrate is D (cm), warpage of said substrate is in the range of 0<H≦70×10⁻⁴ (cm), Z=(thickness of nitride III-V compound semiconductor layers)/(thickness of the substrate), and C (cm⁻¹) is the proportionality constant when the radius of curvature of said substrate ρ (cm) is expressed as 1/ρ=CZ.
 27. The method of manufacturing a semiconductor light emitting device according to claim 26 wherein said warpage of said substrate is in the range of 0<H≦40×10⁻⁴ (cm).
 28. The method of manufacturing a semiconductor light emitting device according to claim 26 wherein said substrate is a sapphire substrate.
 29. The method of manufacturing a semiconductor light emitting device according to claim 26 wherein C=0.20567.
 30. The method of manufacturing a semiconductor light emitting device according to claim 26 wherein said process is a photolithographic process.
 31. The method of manufacturing a semiconductor light emitting device according to claim 26 wherein said process is a polishing process of the bottom surface of said substrate.
 32. A method of manufacturing a semiconductor device using a nitride III-V compound semiconductor substrate in which nitride III-V compound semiconductor layers are formed on a substrate of a material different from those of said nitride III-V compound semiconductor layers, comprising: just before the start of at least one process, said nitride III-V compound semiconductor substrate satisfying 0<y≦0.011 and x≧450 μm when thickness of said substrate is x (μm) and thickness of said nitride III-V compound semiconductor layers is y (μm).
 33. The method of manufacturing a semiconductor device according to claim 32 wherein said x is in the range of 450 μm≦x<1000 μm.
 34. The method of manufacturing a semiconductor device according to claim 32 wherein said x/y is in the range of 0<y/x≦0.0066.
 35. The method of manufacturing a semiconductor device according to claim 34 wherein said x is in the range of 450 μm≦x<1000 μm.
 36. The method of manufacturing a semiconductor device according to claim 34 wherein said substrate is a sapphire substrate.
 37. A method of manufacturing a semiconductor device using a nitride III-V compound semiconductor substrate in which nitride III-V compound semiconductor layers are formed on a substrate of a material different from those of said nitride III-V compound semiconductor layers, comprising: just before the start of at least one process, the relation 0<D<(2/CZ)cos⁻¹(1-HCZ) being satisfied when the maximum dimension of said substrate is D (cm), warpage of said substrate is in the range of 0<H≦70×10⁻⁴ (cm), Z=(thickness of nitride III-V compound semiconductor layers)/(thickness of the substrate), and C (cm⁻¹) is the proportionality constant when the radius of curvature of said substrate ρ (cm) is expressed as 1/ρ=CZ.
 38. The method of manufacturing a semiconductor device according to claim 37 wherein said warpage of said substrate is in the range of 0<H≦40×10⁻⁴ (cm).
 39. The method of manufacturing a semiconductor device according to claim 37 wherein said substrate is a sapphire substrate.
 40. The method of manufacturing a semiconductor device according to claim 37 wherein C=0.20567. 